Configuring a run

Run setup

The panel that holds every per-run choice, and how it relates to your saved defaults.

Run setup is the panel that holds every choice a run makes: mode, tools, models, output language and target device. It slides in from the right and applies to the run you are about to start.

Opening it

Two ways in, both opening the same panel:

The small line above the composer that summarises the current run, reading something like Verilog · AMD / Xilinx. It is a button.
Run setup at the bottom of the Tools menu.

The panel slides in over the right-hand column and closes with the button in its top corner. Changes take effect on the next run you start; there is nothing to save.

Run setup

Configure this generation.

Mode

AgentPlan

Context & retrieval

Web SearchLive results from the open web

Exa SearchSemantic search over datasheets & papers

IP Core LibraryReuse verified cores from the vendor IP catalog

Knowledge BaseRAG over your uploaded specs & PDFs

Verification

Auto-VerifyCompile & simulate the module against its testbench

Exhaustive VerificationCorner-case test plan · golden reference model · coverage guard

ReflectionIf the first simulation fails, a second model reviews and repairs the RTL

Generation

ModelBalanced

Output language

VerilogVHDL

Target device

AMD / XilinxEstimated on 7-series LUTsIntel / AlteraEstimated on MAX 10 LUTs

The Run setup panel. Every control here affects the next run only.

What is in it

Section	What it controls
Mode	Agent or Plan; see Agent mode and Plan mode.
Context & retrieval	The four switches that decide what the run may read; see Tools overview.
Verification	Auto-Verify, Exhaustive Verification and Reflection.
Generation	Balanced or Powerful; see Choosing models. Reasoning depth is set on the composer; see Reasoning effort.
Output language	Verilog or VHDL; see Language and target device.
Target device	The vendor family the synthesis estimate is measured against.

The quick controls on the composer

The three things people change most often are also on the composer itself, so you rarely need the panel: the Agent / Plan toggle, the model picker, and Tools. The tools menu is the same set of switches in a shorter form.

Context & retrieval

Web Search

✓Exa Search

IP Core Library

Knowledge Base (RAG)

Verification

✓Auto-Verify

✓Exhaustive Verification

Reflection

The Tools menu. The count on the button is how many switches are currently on.

Per-run choices and saved defaults

Run setup changes the run in front of you. To change what every new chat starts with, open Settings and use the Run defaults section; it holds the same controls and writes them to your saved defaults.

Tip

If you always want Auto-Verify on, set it in Settings rather than switching it on every time. Run setup then only exists for the exceptions.

When a control is locked

Some combinations are not valid, and the interface removes the choice instead of letting you make it and then rejecting the run:

Situation	What changes
Project mode	The mode toggle becomes a fixed Agent label, and the language is Verilog.
Agent mode	VHDL is unavailable; Agent mode is Verilog only.
VHDL selected	IP Core Library and Knowledge Base are unavailable for that run.
Debug or Optimize	The mode becomes a fixed Agent label and every tool switch is disabled, because those runs choose their own tools; see Build, Debug and Optimize.
Auto-Verify off	Exhaustive Verification goes off with it; it is a simulation strategy and has nothing to run without a simulation.
IP Core Library on	Exhaustive Verification is unavailable, because a module that instantiates a vendor core cannot be compiled on its own.

Heads up

The tool switches only apply to a Plan-mode Build run. Everywhere else they are drawn greyed out with the reason underneath and the Tools badge counts zero, so a switch that looks live really is being used.